(China (Mainland))
Product Summary
The CY7C1305TV25-167BZC is a 1.8V Synchronous Pipelined SRAM equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The CY7C1305TV25-167BZC has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.
Parametrics
CY7C1305TV25-167BZC absolute maximum ratings: (1)Storage Temperature : –65°C to +150°C; (2)Ambient Temperature with Power Applied : –55°C to +125°C; (3)Supply Voltage on VDD Relative to GND : –0.5V to +2.9V; (4)DC Applied to Outputs in High-Z State : –0.5V to VDDQ + 0.5V; (5)DC Input Voltage[11]: –0.5V to VDDQ + 0.5V; (6)Current into Outputs (LOW): 20 mA; (7)Static Discharge Voltage : > 2001V (per MIL-STD-883, Method 3015); (8)Latch-Up Current : > 200 mA.
Features
CY7C1305TV25-167BZC features: (1)4-Word Burst for reducing the address bus frequency; (2)Double Data Rate (DDR)interfaces on both Read & Write Ports (data transferred at 333 MHz)@167 MHz; (3)Two input clocks (K and K)for precise DDR timing: SRAM uses rising edges only; (4)Two output clocks (C and C)accounts for clock skew and flight time mismatching; (5)Single multiplexed address input bus latches address inputs for both Read and Write ports; (6)Separate Port Selects for depth expansion; (7)Synchronous internally self-timed writes; (8)1.8V core power supply with HSTL Inputs and Outputs; (9)13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix); (10)Variable drive HSTL output buffers; (11)Expanded HSTL output voltage (1.4V–1.9V); (12)JTAG Interface.
Diagrams
| Image | Part No | Mfg | Description |  |
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 CY7C1305TV25-167BZC |
Cypress Semiconductor |
SRAM NVSRAM 167 MHz 2.5V |
Data Sheet |
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