CY7C1313TV18-250BZC

CY7C1313TV18-250BZC, Synchronous Pipelined SRAM, 2.9 V, 200 mA, BGA

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Price:: US $23.93~24.59 / piece [Get Latest Price]

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Qty (lots)	Price/lot
1 ~ 100 :	24.59 / Piece
110 ~ 500 :	24.10 / Piece
510 ~ 2000 :	23.93 / Piece

PartNumber:: CY7C1313TV18-250BZC

Brand:: Cypress Semiconductor - Cypress | Pack: BGA | D/C: 11+

Availability:: Supply Ability: 1/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2013-04-28

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Part Number:CY7C1313TV18-250BZC
US $23.93 - 24.59
Quantity:

piece

Product Summary

The CY7C1313TV18-250BZC is a 1.8 V Synchronous Pipelined SRAM, equipped with QDR IIarchitecture. QDR II architecture consists of two separate ports:the read port and the write port to access the memory array. The CY7C1313TV18-250BZC has dedicated data outputs to support read operationsand the write port has dedicated data inputs to support writeoperations. All synchronous inputs pass through input registers controlled bythe K or K input clocks. All data outputs pass through outputregisters controlled by the C or C (or K or K in a single clockdomain) input clocks. Writes are conducted with on-chipsynchronous self-timed write circuitry.

Parametrics

CY7C1313TV18-250BZC absolute maximum ratings: (1)Storage temperature : –65 °C to +150 °C; (2)Ambient temperature with power applied: –55 °C to +125 °C; (3)Supply voltage on VDD relative to GND: –0.5 V to +2.9 V; (4)Supply voltage on VDDQ relative to GND: –0.5 V to +VDD; (5)DC applied to outputs in High Z : –0.5 V to VDDQ + 0.5 VDC; (6)input voltage[17] : –0.5 V to VDD + 0.5 V; (7)Current into outputs (LOW): 20 mA; (8)Static discharge voltage (MIL-STD-883, M. 3015): > 2001 V; (9)Latch up current: > 200 mA.

Features

CY7C1313TV18-250BZC features: (1)Two output clocks (C and C)accounts for clock skew and flight time mismatching; (2)Echo clocks (CQ and CQ)simplify data capture in high speed systems; (3)Single multiplexed address input bus latches address inputs for both Read and Write ports; (4)Separate Port Selects for depth expansion; (5)Synchronous internally self-timed writes; (6)Available in ×8, ×18, and ×36 configurations; (7)Full data coherancy providing most current data; (8)Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd); (9)13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix); (10)Variable drive HSTL output buffers; (11)JTAG 1149.1 Compatible test access port; (12)Delay Lock Loop (DLL)for accurate data placement.