CY7C1360S-200BGC

CY7C1360S-200BGC, SRAM, 20 mA, 2001V, 250 MHz, BGA

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Price:: US $23.77~25.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
1 ~ 100 :	25.00 / Piece
110 ~ 500 :	24.26 / Piece
510 ~ 1000 :	23.77 / Piece

PartNumber:: CY7C1360S-200BGC

Brand:: Cypress Semiconductor - Cypress | Pack: BGA | D/C: 11+

Availability:: Supply Ability: 1/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-05-06

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Part Number:CY7C1360S-200BGC
US $23.77 - 25.00
Quantity:

piece

Product Summary

The CY7C1360S-200BGC is a SRAM. The CY7C1360S-200BGC integrates 256K x 36 and 512K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The CY7C1360S-200BGC’s synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Parametrics

CY7C1360S-200BGC absolute maximum ratings: (1)Storage Temperature:–65 to +150℃; (2)Ambient Temperature with Power Applied:–55 to +125℃; (3)Supply Voltage on VDD Relative to GND: ; (4)Supply Voltage on VDDQ Relative to GND: –0.5V to +VDD; (5)DC Voltage Applied to Outputs in Tri-State:–0.5V to VDDQ + 0.5V; (6)DC Input Voltage: –0.5V to VDD + 0.5V; (7)Current into Outputs (LOW): 20 mA; (8)Static Discharge Voltage: > 2001V; (9)Latch-up Current: > 200 mA.

Features

CY7C1360S-200BGC features: (1)Supports bus operation up to 250 MHz; (2)Available speed grades are 250, 200, and 166 MHz; (3)Registered inputs and outputs for pipelined operation; (4)3.3V core power supply (VDD); (5)2.5V/3.3V I/O operation (VDDQ); (6)Fast clock-to-output times: 2.8 ns (for 250-MHz device); (7)Provide high-performance 3-1-1-1 access rate; (8)User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences; (9)Separate processor and controller address strobes; (10)Synchronous self-timed writes; (11)Asynchronous output enable; (12)Single Cycle Chip Deselect; (13)Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package; (14)TQFP Available with 3-Chip Enable and 2-Chip Enable; (15)IEEE 1149.1 JTAG-Compatible Boundary Scan.