Product Summary

The CY7C1314KV18-250BZXC is a 1.8 V Synchronous Pipelined SRAM, equipped with QDR IIarchitecture. QDR II architecture consists of two separate ports:the read port and the write port to access the memory array. The CY7C1314KV18-250BZXC has dedicated data outputs to support read operationsand the write port has dedicated data inputs to support writeoperations. All synchronous inputs pass through input registers controlled bythe K or K input clocks. All data outputs pass through outputregisters controlled by the C or C (or K or K in a single clockdomain) input clocks. Writes are conducted with on-chipsynchronous self-timed write circuitry.

Parametrics

CY7C1314KV18-250BZXC absolute maximum ratings: (1)Storage temperature : –65 °C to +150 °C; (2)Ambient temperature with power applied: –55 °C to +125 °C; (3)Supply voltage on VDD relative to GND: –0.5 V to +2.9 V; (4)Supply voltage on VDDQ relative to GND: –0.5 V to +VDD; (5)DC applied to outputs in High Z : –0.5 V to VDDQ + 0.5 VDC; (6)input voltage[17] : –0.5 V to VDD + 0.5 V; (7)Current into outputs (LOW): 20 mA; (8)Static discharge voltage (MIL-STD-883, M. 3015): > 2001 V; (9)Latch up current: > 200 mA.

Features

CY7C1314KV18-250BZXC features: (1)Two input clocks for output data (C and C)to minimize clock skew and flight time mismatches; (2)Echo clocks (CQ and CQ)simplify data capture in high-speed systems; (3)Single multiplexed address input bus latches address inputs for both read and write ports; (4)Separate port selects for depth expansion; (5)Synchronous internally self-timed writes; (6)QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH; (7)Operates similar to QDR I device with one cycle read latency when DOFF is asserted LOW; (8)Available in ×8, ×9, ×18, and ×36 configurations; (9)Full data coherency, providing most current data; (10)Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD; (11)Supports both 1.5 V and 1.8 V I/O supply; (12)Available in 165-ball FBGA package (13 × 15 × 1.4 mm); (13)Offered in both Pb-free and non Pb-free packages; (14)Variable drive HSTL output buffers; (15)JTAG 1149.1 compatible test access port; (16)PLL for accurate data placement.

Diagrams

CY7C1314KV18-250BZXC pin connection 

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
CY7C1314KV18-250BZXC
CY7C1314KV18-250BZXC

Cypress Semiconductor

SRAM 18Mb 1.8V 512K x 36

Data Sheet

0-86: $14.69
86-100: $13.77
100-500: $12.21
CY7C1314KV18-250BZXCT
CY7C1314KV18-250BZXCT

Cypress Semiconductor

SRAM 18Mb 1.8V 1Mb x 18

Data Sheet

0-753: $12.25
753-1000: $11.75